Fujitsu 8FX Hardware Manual page 21

Page
498
CHAPTER 24 I
INTERFACE
24.3 Channel
■ Channel of I
Table 24.3-2
531 CHAPTER 25 EXAMPLE OF
to SERIAL PROGRAMMING
534 CONNECTION
568 CHAPTER 26 DUAL OPERATION
FLASH MEMORY
26.8.2 Flash Memory Status Register
(FSR)
■ Register Functions
588 CHAPTER 27 NON-VOLATILE
REGISTER (NVR) INTERFACE
27.3.4 Watchdog Timer Selection ID
Register (Upper/Lower)
(WDTH/WDTL)
■ Register Configuration
Revisions (For details, see their respective pages.)
2 Corrected the register name of the IBCR0n register.
C BUS
I
2
C Bus Interface I
Corrected the register name of the IBCR1n register.
I
I
Corrected the register name of the IBSRn register.
I
I
Corrected the register name of the IDDRn register.
I
I
Corrected the register name of the IAARn register.
I
I
Corrected the register name of the ICCRn register.
I
I
New chapter
Corrected Figure 26.8-1.
Corrected the R/W attribute of the WDTH[7:0] bits in the
WDTH register.
R/W
Corrected the R/W attribute of the WDTL[7:0] bits in the
WDTL register.
R/W
2
C bus control register 0
2
C bus control register 0 ch. n
2
C bus control register 1
2
C bus control register 1 ch. n
2
C bus status register
2
C bus status register ch. n
2
C data register
2
C data register ch. n
2
C address register
2
C address register ch. n
2
C clock control register
2
C clock control register ch. n
R
R
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