I 2 C Bus Status Register Ch. N (Ibsrn) - Fujitsu 8FX Hardware Manual

MB95630H Series
2
24.7.3 I C Bus Status Register ch. n (IBSRn)
2
The I C bus status register ch. n (IBSRn) indicates the status of the I
interface.
■ Register Configuration
bit 7
Field BB
Attribute R
Initial value 0
■ Register Functions
[bit7] BB: Bus busy bit
This bit indicates the bus state.
bit7
Reading "0"
Reading "1"
[bit6] RSC: Repeated START condition detection bit
This bit detects the repeated START condition.
This bit is set to "1" when a repeated START condition is detected.
If one of the following conditions is satisfied, this bit is set to "0".
• "0" is written to the IBCR1n:INT bit.
• In slave mode, the slave address does not match the address set in the IAARn register.
• In slave mode, the slave address matches the address set in the IAARn register but the IBCR0n:AACKX bit
is set to "1".
• In slave mode, the device receives a general call address, but the IBCR1n:GACKE bit is set to "0".
• A STOP condition is detected.
bit6
Reading "0"
Reading "1"
[bit5] Undefined bit
The read value of this bit is always "0". Writing a value to this bit has no effect on operation.
MN702-00009-2v0-E
6 5
RSC —
R —
0 0
Indicates that a STOP condition has been detected and the bus has entered the idle state.
Indicates that a START condition has been detected and the bus has entered the busy state.
Indicates that no repeated START condition has been detected.
Indicates that the bus is in use and a repeated START condition has been detected.
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER 24 I
4 3
LRB TRX
R R
0 0
Details
Details
2
C BUS INTERFACE
24.7 Registers
2
C bus
2 1
AAS GCA
R R
0 0
0
FBT
R
0
521