I 2 C Clock Control Register Ch. N (Iccrn) - Fujitsu 8FX Hardware Manual

2
CHAPTER 24 I C BUS INTERFACE
24.7 Registers
2
24.7.6 I C Clock Control Register ch. n (ICCRn)
2
The I C clock control register ch. n (ICCRn) register enables the I
and selects the shift clock frequency.
■ Register Configuration
bit 7
Field DMBP
Attribute R/W
Initial value 0
■ Register Functions
[bit7] DMBP: Divider m bypass bit
This bit is used to bypass the divider m to generate the shift clock frequency.
Writing "0" to this bit sets the value set in the CS[4:3] bits as the divider m value (m = ICCRn:CS[4:3]).
When "1" is written to this bit, the divider m is to be bypassed.
Do not write "1" to this bit when the value of divider n is "4" (ICCRn:CS[2:0] = 0b000).
bit7
Writing "0"
Writing "1"
[bit6] Undefined bit
The read value of this bit is always "0". Writing a value to this bit has no effect on operation.
2
[bit5] EN: I C bus interface operation enable bit
2
This bit enables the I
Writing "0" to this bit disables the I
• AACKX, INTS, and WUE bits in the IBCR0n register
• All bits in the IBCR1n register except the BER and BEIE bits
• All bits in the IBSRn register
Writing "1" to this bit enables the I
If one of the following conditions is satisfied, this bit is set to "0".
• "0" is written to this bit.
• The BER bit in the IBCR1n register is set to "1".
bit5
Writing "0"
Writing "1"
526
6 5
— EN
— R/W
0 0
The settings of ICCRn:CS[4:3] (clock divide m) are valid.
The settings of ICCRn:CS[4:3] (clock divide m) are invalid.
C bus interface operation.
2
C bus interface operation and clears the following bits to "0".
2
C bus interface operation.
2
Disables the I C bus interface operation.
2
Enables the I C bus interface operation.
FUJITSU SEMICONDUCTOR LIMITED
4 3
CS4 CS3
R/W R/W
0 0
Details
Details
MB95630H Series
2
C operation
2 1
CS2 CS1
R/W R/W
0 0
MN702-00009-2v0-E
0
CS0
R/W
0