Fujitsu 8FX Hardware Manual page 96

CHAPTER 5 INTERRUPTS
5.1 Interrupts
The interrupt level setting bits are compared with the interrupt level bits in the condition code
register (CCR:IL[1:0]).
If the interrupt level of an interrupt request is 3, the CPU ignores that interrupt request.
Table 5.1-1 shows the relationships between interrupt level setting bits and interrupt levels.
Table 5.1-1 Relationships Between Interrupt Level Setting Bits and Interrupt Levels
LXX[1:0]
00
01
10
11
XX:00 to 23 Number of an interrupt request
While the main program is being executed, the interrupt level bits in the condition code register
(CCR:IL[1:0]) are "0b11".
74
Interrupt level
0
1
2
3
FUJITSU SEMICONDUCTOR LIMITED
MB95630H Series
Priority
Highest
Lowest (No interrupt)
MN702-00009-2v0-E