Flash Memory Status Register 2 (Fsr2) - Fujitsu 8FX Hardware Manual

MB95630H Series
26.8.1

Flash Memory Status Register 2 (FSR2)

This section describes the Flash memory status register 2 (FSR2).
■ Register Configuration
bit 7
Field PEIEN
Attribute R/W
Initial value 0
■ Register Functions
[bit7] PEIEN: PGMEND interrupt enable bit
This bit enables or disables the generation of interrupt requests triggered by the completion of Flash memory
programming.
bit7
Writing "0"
Writing "1"
[bit6] PGMEND: PGMEND interrupt request flag bit
This bit indicates the completion of Flash memory programming.
The PGMEND bit is set to "1" upon completion of the Flash memory automatic algorithm.
An interrupt request is generated when the PGMEND bit is set to "1", provided that generating an interrupt
request upon completion of Flash memory programming has been enabled (FSR2:PEIEN = 1).
When the PGMEND bit is set to "0" after Flash memory programming is completed, further Flash memory
programming/erasing is disabled. Writing a reset command can make the Flash memory return to the normal
command state.
When Flash memory programming fails (FSR3:HANG = 1), the PGMEND bit is cleared to "0".
Writing "0" to this bit clears it.
Writing "1" to this bit has no effect on operation.
When read by the read-modify-write (RMW) type of instruction, this bit always returns "1".
bit6
Reading "0"
Reading "1"
Writing "0"
Writing "1"
MN702-00009-2v0-E
6 5
PGMEND PTIEN
R/W R/W
0 0
Disables the interrupt request upon completion of Flash memory programming
(FSR2:PGMEND = 1).
Enables the interrupt request upon completion of Flash memory programming
(FSR2:PGMEND = 1).
Indicates that the device is in the command input wait state or Flash memory programming is in
progress.
Indicates that Flash memory programming has been completed.
Clears this bit.
Has no effect on operation.
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER 26 DUAL OPERATION FLASH MEMORY
4 3
PGMTO EEIEN
R/W R/W
0 0
Details
Details
26.8 Registers
2 1
ERSEND ETIEN
R/W R/W
0 0
0
ERSTO
R/W
0
563