Fujitsu 8FX Hardware Manual page 491

MB95630H Series
The TDRE bit is set at the point indicated in Figure 22.6-7 or Figure 22.6-8 if the preceding
piece of transmit data does not exist in the transmission shift register.
Figure 22.6-7 Setting Timing 1 for Transmit Data Register Empty Flag Bit (TDRE)
TXE = "1"
Writing of
transmit data
UOn
TDRE
Transmit
interrupt
Figure 22.6-8 Setting Timing 2 for Transmit Data Register Empty Flag Bit (TDRE)
TXE
Writing of
transmit data
UOn
TDRE
Transmit
interrupt
● Concurrent transmission and reception
In clock asynchronous mode (UART), transmission and reception can be performed
independently. Therefore, transmission and reception can be performed at the same time or
even with transmitting and receiving frames overlapping each other in shifted phases.
MN702-00009-2v0-E
(When TXE Is "1")
D0 D1
Data transfer from UART/SIO serial output data register ch. n (TDRn) to transmission
shift register is performed in one machine clock (MCLK) cycle.
(When TXE Is Switched from "0" to "1")
D0
FUJITSU SEMICONDUCTOR LIMITED
22.6 Operations and Setting Procedure Example
D2 D3
D1 D2
CHAPTER 22 UART/SIO
D3
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