(Tras[2:0] = 001, Trc[2:0] = 001) - Hitachi SH7750 Hardware Manual

Sh7750 series superh risc engine

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(SA: IO ← memory)

(SA: IO → memory)

Notes: IO: DACK device

SA: Single address DMA transfer

DA: Dual address DMA transfer

DACK set to active-high

Figure 22.50 DRAM Bus Cycle: DRAM CAS-Before-RAS Refresh

(TRAS[2:0] = 001, TRC[2:0] = 001)

Rev. 6.0, 07/02, page 913 of 986

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