Clock And Control Signal Timing; Table 22.25 Clock And Control Signal Timing (Hd6417750Rbp240) - Hitachi SH7750 Hardware Manual

22.3.1

Clock and Control Signal Timing

Table 22.25 Clock and Control Signal Timing (HD6417750RBP240)

V = 3.0 to 3.6 V, V
DDQ
Item
EXTAL PLL1 6-times/PLL2
clock input operation
frequency
PLL1 12-times/PLL2
operation
PLL1/PLL2 not operating
EXTAL clock input cycle time
EXTAL clock input low-level pulse width
EXTAL clock input high-level pulse width t
EXTAL clock input rise time
EXTAL clock input fall time
CKIO clock PLL1/PLL2 operating
output
PLL1/PLL2 not operating
CKIO clock output cycle time
CKIO clock output low-level pulse width
CKIO clock output high-level pulse width
CKIO clock output rise time
CKIO clock output fall time
CKIO clock output low-level pulse width
CKIO clock output high-level pulse width
Power-on oscillation settling time
Power-on oscillation settling time/mode
settling
SCK2 reset setup time
SCK2 reset hold time
MD reset setup time
MD reset hold time
RESET assert time
PLL synchronization settling time
Standby return oscillation settling time 1
Standby return oscillation settling time 2
Rev. 6.0, 07/02, page 844 of 986
= 1.5 V, T = –20 to +75°C, C
DD a
Symbol
f
f
f
t
t
t
t
f
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
= 30 pF
L
Min
16
EX
14
EX
1
EX
30
EXcyc
3.5
EXL
3.5
EXH
—
EXr
—
EXf
25
OP
1
OP
8.3
cyc
1
CKOL1
1
CKOH1
—
CKOr
—
CKOf
3
CKOL2
3
CKOH2
10
OSC1
10
OSCMD
20
SCK2RS
20
SCK2RH
3
MDRS
20
MDRH
20
RESW
200
PLL
3
OSC2
3
OSC3
Max Unit Figure
34 MHz
20
34
1000 ns 22.1
— ns 22.1
— ns 22.1
4 ns 22.1
4 ns 22.1
120 MHz
34 MHz
1000 ns 22.2(1)
— ns 22.2(1)
— ns 22.2(1)
3 ns 22.2(1)
3 ns 22.2(1)
— ns 22.2(2)
— ns 22.2(2)
— ms 22.3, 22.5
— ms 22.3, 22.5
— ns 22.11
— ns 22.3, 22.5, 22.11
— t 22.12
cyc
— ns 22.3, 22.5, 22.12
— t 22.3, 22.4, 22.5,
cyc
22.6, 22.11
µs
— 22.9, 22.10
— ms 22.4, 22.6
— ms 22.7