Hitachi SH7750 Hardware Manual page 471

CKIO
Bank
Precharge-sel
Address
RD/
DQMn
D63–D0
(read)
CKE
DACKn
(SA: IO → memory)
Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
Figure 13.31 Basic Timing for Synchronous DRAM Single Write
Tr Trw Tc1
Row
Row
Row
c1
Tc2 Tc3 Tc4
H/L
c1
Rev. 6.0, 07/02, page 421 of 986
Trw1 Trw1 Tpc