Figure 3.10 Flowchart Of Memory Access Using Utlb - Hitachi SH7750 Hardware Manual

VA is
in P4 area
On-chip I/O access
No
Data TLB miss
exception
00 or
01
W
Data TLB protection
violation exception
Cache access
in copy-back mode

Figure 3.10 Flowchart of Memory Access Using UTLB

Rev. 6.0, 07/02, page 76 of 986
Data access to virtual address (VA)
VA is VA is
in P2 area in P1 area
0
CCR.OCE?
1
0
CCR.CB?
1
VPNs match
and V = 1
Yes
0 (User)
PR?
11
10
R/W? R/W?
R R
Initial page write
and CCR.OCE = 1
0
Cache access
in write-through mode
No
MMUCR.AT = 1
CCR.WT?
0
1
SH = 0
No
and (MMUCR.SV = 0 or
SR.MD = 0)
VPNs match
No
and ASIDs match and
V = 1
Only one
entry matches
SR.MD?
Memory access
01 or 11
W W
R/W?
R
1
D?
0
exception
C = 1
No
Yes
WT?
1
VA is in P0, U0,
or P3 area
Yes
Yes
Yes
No
Yes
Data TLB multiple
hit exception
1 (Privileged)
00 or 10
W
R/W?
R
Data TLB protection
violation exception
Memory access
(Non-cacheable)