Hitachi SH7750 Hardware Manual page 80

Table 1.3 Pin Functions (cont)
Pin
No. Pin Name I/O
194 TDO O
195 VDD Power
196 VSS Power
197 TMS I
198 TCK I
199 TDI I
TRST
200 I
201 VDD-PLL2 Power
202 VSS-PLL2 Power
203 VDD-PLL1 Power
204 VSS-PLL1 Power
205 VDD-CPG Power
206 VSS-CPG Power
207 XTAL O
208 EXTAL I
I: Input
O: Output
I/O: Input/output
Power: Power supply
Notes: 1. Except in hardware standby mode, supply power to all power pins. In hardware standby
mode, supply power to RTC as a minimum.
2. Power must be supplied to VDD-PLL1/2 and VSS-PLL1/2 regardless of whether or not
the on-chip PLL circuits are used.
3. Power must be supplied to VDD-CPG and VSS-CPG regardless of whether or not the
on-chip crystal resonator is used.
4. Power must be supplied to VDD-RTC and VSS-RTC regardless of whether or not the
on-chip RTC is used.
5. VSSQ, VSS, VSS-RTC, VSS-PLL1/2, and VSS-CPG are connected inside the package.
6. In the SH7750S and SH7750R, at least the RTC power supply must be supplied in
hardware standby mode.
7. The RD2, RD/WR2, CKIO2, and CKIO2ENB pins are not provided on the QFP
package.
8. For a QFP package, the maximum operating frequency of the external bus is 84 MHz.
* Hardware standby request (SH7750S and SH7750R). In the SH7750, pull up to 3.3 V.
Rev. 6.0, 07/02, page 30 of 986
Function Reset
Data out
(H-UDI)
Internal VDD
Internal GND
(0 V)
Mode (H-UDI)
Clock (H-UDI)
Data in (H-UDI)
Reset (H-UDI)
PLL2 VDD (3.3V)
PLL2 GND (0V)
PLL1 VDD (3.3V)
PLL1 GND (0V)
CPG VDD (3.3V)
CPG GND (0V)
Crystal resonator
External input
clock/crystal
resonator
Memory Interface
SRAM DRAM SDRAM PCMCIA MPX