Hitachi SH7750 Hardware Manual page 83

Table 1.4 Pin Functions (cont)
Pin
No. No. Pin Name
BREQ/
61 R2
BSACK
62 T3 D8
63 U2 D7
64 R4 CKE
65 T5 VDDQ
66 T2 VSSQ
WE5/CAS5/
67 R5
DQM5
WE4/CAS4/
68 P5
DQM4
WE1/CAS1/
69 U5
DQM1
WE0/CAS0/
70 P6
DQM0
71 R6 A17
72 P4 VDDQ
73 T6 VSSQ
74 N6 A16
75 U6 A15
76 P7 VDD
77 R7 VSS
78 M6 A14
79 T7 A13
80 N7 VDDQ
81 U7 VSSQ
82 R8 A12
83 P8 A11
84 U8 A10
85 N8 VDDQ
86 T8 VSSQ
87 M8 A9
88 R9 A8
I/O Function
I Bus request/bus
acknowledge
I/O Data
I/O Data
O Clock output
enable
Power IO VDD (3.3 V)
Power IO GND (0 V)
O D47–D40 select
signal
O D39–D32 select
signal
O D15–D8 select
signal
O D7–D0 select
signal
O Address
Power IO VDD (3.3 V)
Power IO GND (0 V)
O Address
O Address
Power Internal VDD
(1.5 V)
Power Internal GND
(0 V)
O Address
O Address
Power IO VDD (3.3 V)
Power IO GND (0 V)
O Address
O Address
O Address
Power IO VDD (3.3 V)
Power IO GND (0 V)
O Address
O Address
Reset SRAM DRAM
WE5 CAS5
WE4 CAS4
WE1 CAS1
WE0 CAS0
Memory Interface
SDRAM PCMCIA MPX
CKE
DQM5
DQM4
WE1
DQM1
DQM0
Rev. 6.0, 07/02, page 33 of 986
A8
A7