Hitachi SH7750 Hardware Manual page 88

Table 1.4 Pin Functions (cont)
Pin
No. No. Pin Name
198 D11 VSS
199 C11 A18
200 F12 A19
201 B11 VDDQ
202 E11 VSSQ
203 A11 A20
204 F11 A21
205 C10 A22
206 D10 A23
207 A10 VDDQ
208 E10 VSSQ
209 B10 A24
210 F10 A25
211 C9 MD3/CE2A I/O
212 E9 MD4/CE2B I/O
213 A9 VDDQ
214 F9 VSSQ
215 D9 MD5/RAS2 I/O
216 B9 DACK0
217 F8 DACK1
218 A8 A0
219 E8 VDDQ
220 C8 VSSQ
221 D8 A1
222 B8 STATUS0
223 F7 STATUS1
224 A7 MD6/
IOIS16
225 E7 VDDQ
226 C7 VSSQ
Rev. 6.0, 07/02, page 38 of 986
I/O Function
Power Internal GND
(0 V)
O Address
O Address
Power IO VDD (3.3 V)
Power IO GND (0 V)
O Address
O Address
O Address
O Address
Power IO VDD (3.3 V)
Power IO GND (0 V)
O Address
O Address
Mode/
PCMCIA-CE
Mode/
PCMCIA-CE
Power IO VDD (3.3 V)
Power IO GND (0 V)
Mode/RAS
(DRAM)
O DMAC0 bus
acknowledge
O DMAC1 bus
acknowledge
O Address
Power IO VDD (3.3 V)
Power IO GND (0 V)
O Address
O Status
O Status
I Mode/IOIS16
(PCMCIA)
Power IO VDD (3.3 V)
Power IO GND (0 V)
Reset SRAM DRAM
MD3
MD4
RAS2
MD5
MD6
Memory Interface
SDRAM PCMCIA MPX
CE2A
CE2B
IOIS16