Figure 22.32 Synchronous Dram Normal Write Bus Cycle: Write Command, Burst (Trwl[2:0] = 010) - Hitachi SH7750 Hardware Manual

Sh7750 series superh risc engine

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Precharge-sel

(SA: IO → memory)

Notes: In the case of SA-DMA only, the (Tnop) cycle is inserted, and the DACKn signal is output as shown by the

solid line. In a normal write, the (Tnop) cycle is omitted and the DACKn signal is output as shown by the

dotted line.

IO: DACK device

SA: Single address DMA transfer

DA: Dual address DMA transfer

DACK set to active-high

Figure 22.32 Synchronous DRAM Normal Write Bus Cycle: WRITE Command, Burst

Rev. 6.0, 07/02, page 894 of 986

Normal write

(TRWL[2:0] = 010)

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