Fifo Data Count Register (Scfdr2) - Hitachi SH7750 Hardware Manual

Bit 0—Loopback Test (LOOP): Internally connects the transmit output pin (TxD2) and receive
input pin (RxD2), and the RTS2 pin and CTS2 pin, enabling loopback testing.
Bit 0: LOOP
0
1

16.2.10 FIFO Data Count Register (SCFDR2)

SCFDR2 is a 16-bit register that indicates the number of data bytes stored in SCFTDR2 and
SCFRDR2.
The upper 8 bits show the number of transmit data bytes in SCFTDR2, and the lower 8 bits show
the number of receive data bytes in SCFRDR2.
SCFDR2 can be read by the CPU at all times.
Bit:
Initial value:
R/W:
These bits show the number of untransmitted data bytes in SCFTDR2. A value of H'00 indicates
that there is no transmit data, and a value of H'10 indicates that SCFTDR2 is full of transmit data.
Bit:
Initial value:
R/W:
These bits show the number of receive data bytes in SCFRDR2. A value of H'00 indicates that
there is no receive data, and a value of H'10 indicates that SCFRDR2 is full of receive data.
Rev. 6.0, 07/02, page 678 of 986
Description
Loopback test disabled
Loopback test enabled
15 14 13
— — —
0 0
R R
7 6
— — —
0 0
R R
12 11
T4 T3
0 0 0
R R R
5 4 3
R4 R3
0 0 0
R R R
(Initial value)
10 9 8
T2 T1 T0
0 0 0
R R R
2 1 0
R2 R1 R0
0 0 0
R R R