Hitachi SH7750 Hardware Manual page 381

Bits 13 to 11—Area 0 Burst ROM Control (A0BST2–A0BST0): These bits specify whether
burst ROM interface is used in area 0. When burst ROM interface is used, they also specify the
number of accesses in a burst. If area 0 is an MPX interface area, these bits are ignored.
Bit 13: A0BST2 Bit 12: A0BST1
0 0
1
1 0
1
Note: * Settable only for SH7750R.
Bit 11: A0BST0 Description
0 Area 0 is accessed as SRAM interface
1 Area 0 is accessed as burst ROM
interface (4 consecutive accesses)
Can be used with 8-, 16-, 32-, or 64*-bit
bus width
0 Area 0 is accessed as burst ROM
interface (8 consecutive accesses)
Can only be used with 8-, 16-, or 32-bit
bus width
1 Area 0 is accessed as burst ROM
interface (16 consecutive accesses)
Can only be used with 8- or 16-bit bus
width. Do not specify for 32-bit bus width
0 Area 0 is accessed as burst ROM
interface (32 consecutive accesses)
Can only be used with 8-bit bus width
1 Reserved
0 Reserved
1 Reserved
(Initial value)
Rev. 6.0, 07/02, page 331 of 986