Hitachi SH7750 Hardware Manual page 399

Sh7750 series superh risc engine

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Bits 5 to 3—Area 0 Wait Control (A0W2 to A0W0): These bits specify the number of wait

states to be inserted for area 0. For details on MPX interface setting, see table 13.6, MPX Interface

is Selected (Areas 0 to 6).

Bits 2 to 0—Area 0 Burst Pitch (A0B2–A0B0): These bits specify the number of wait states to

be inserted afterwards the second data access in a burst transfer with the burst ROM interface

Inserted Wait States

15 (Initial value)

Wait States Inserted from

Second Data Access Onward

7 (Initial value)

Burst Cycle (Excluding First Cycle)

Rev. 6.0, 07/02, page 349 of 986

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