Hitachi SH7750 Hardware Manual page 89

Table 1.4 Pin Functions (cont)
Pin
No. No. Pin Name
ASEBRK/
227 E6
BRKACK
228 A6 TDO
229 D7 VDD
230 B7 VSS
231 E5 TMS
232 C6 TCK
233 D6 TDI
TRST
234 A5
CKIO2ENB I
235 D5
236 B6 VDD-PLL2
237 C3 VSS-PLL2
238 C5 VDD-PLL1
239 C4 VSS-PLL1
240 A4 VDD-CPG
241 A1 VSS-CPG
242 A2 XTAL
243 A3 EXTAL
244 B3 NC-1
245 B4 NC-2
246 B5 NC-3
247 B14 NC-4
248 B15 NC-5
249 B16 NC-6
250 C1 NC-7
251 C17 NC-8
252 D1 NC-9
253 D2 NC-10
254 D16 NC-11
255 E16 NC-12
I/O Function
I/O Pin break/
acknowledge
)
(H-UDI
O Data out
(H-UDI)
Power Internal VDD
(1.5 V)
Power Internal GND
(0 V)
I Mode (H-UDI)
I Clock (H-UDI)
I Data in (H-UDI)
I Reset (H-UDI)
CKIO2, RD2,
RD/WR2 enable
Power PLL2 VDD (3.3V)
Power PLL2 GND (0V)
Power PLL1 VDD (3.3V)
Power PLL1 GND (0V)
Power CPG VDD (3.3V)
Power CPG GND (0V)
O Crystal resonator
I External clock/
crystal resonator
Reset SRAM DRAM
Memory Interface
SDRAM PCMCIA MPX
Rev. 6.0, 07/02, page 39 of 986