Hitachi SH7750 Hardware Manual page 84

Table 1.4 Pin Functions (cont)
Pin
No. No. Pin Name
89 N9 A7
90 U9 CKIO
91 M9 VDDQ
92 P9 VSSQ
93 T9 CKIO2
94 M10 A6
95 U10 A5
96 N10 A4
97 R10 VDDQ
98 P10 VSSQ
99 T10 A3
100 M11 A2
101 U11 DRAK1
102 N11 DRAK0
103 R11 VDDQ
104 N12 VSSQ
105 U12 CS3
CS2
106 P11
107 T11 VDD
108 N13 VSS
109 R12 RAS
RD/CASS/
110 P12
FRAME
111 U13 VDDQ
112 P13 VSSQ
113 T12 RD/WR
114 R15 WE2/CAS2/
DQM2/
ICIORD
115 R13 WE3/CAS3/
DQM3/
ICIOWR
Rev. 6.0, 07/02, page 34 of 986
I/O Function
O Address
O Clock output
Power IO VDD (3.3 V)
Power IO GND (0 V)
O CKIO*
O Address
O Address
O Address
Power IO VDD (3.3 V)
Power IO GND (0 V)
O Address
O Address
O DMAC1 request
acknowledge
O DMAC0 request
acknowledge
Power IO VDD (3.3 V)
Power IO GND (0 V)
O Chip select 3
O Chip select 2
Power Internal VDD
(1.5 V)
Power Internal GND
(0 V)
RAS
O
O Read/CAS/
FRAME
Power IO VDD (3.3 V)
Power IO GND (0 V)
O Read/write
O D23–D16 select
signal
O D31–D24 select
signal
Reset SRAM DRAM
CS3
(CS3)
CS2
(CS2)
RAS
OE
RD/WR RD/WR RD/WR
WE2 CAS2
WE3 CAS3
Memory Interface
SDRAM PCMCIA MPX
CKIO
CKIO
CS3 CS3
CS2 CS2
RAS
CAS OE FRAME
RD/WR
ICIORD
DQM2
ICIOWR
DQM3