Caches; Overview; Features; Table 4.1 Cache Features (Sh7750, Sh7750S) - Hitachi SH7750 Hardware Manual

4.1

Overview

4.1.1

Features

An SH7750 or SH7750S has an on-chip 8-kbyte instruction cache (IC) for instructions and 16-
kbyte operand cache (OC) for data. Half of the memory of the operand cache (8 kbytes) may
alternatively be used as on-chip RAM. The features of this cache are summarized in table 4.1
The SH7750R has an on-chip 16-kbyte instruction cache (IC) for instructions and 32-kbyte
operand cache (OC) for data. Half of the memory of the operand cache (16 kbytes) may
alternatively be used as on-chip RAM. When the EMODE bit of the CCR register is 0, the
SH7750R's cache is set to operate in the SH7750/SH7750S-compatible mode and behaves as
shown in table 4.1. The features of the cache when the EMODE bit in the CCR register is 1 are
given in table 4.2. The EMODE bit is initialized to 0 after a power-on reset or manual reset.
For high-speed writing to external memories, the SH7750 series supports 32 bytes × 2 of store
queues (SQ). Table 4.3 lists the features of these SQs.
Table 4.1 Cache Features (SH7750, SH7750S)
Item
Capacity
Type
Line size
Entries
Write method
Table 4.2 Cache Features (SH7750R)
Item
Capacity
Type
Line size
Entries
Write method
Replacement method
Section 4 Caches
Instruction Cache
8-kbyte cache
Direct mapping
32 bytes
256
Instruction Cache
16-kbyte cache
2-way set-associative
32 bytes
256 entries/way
LRU (least-recently-used) algorithm LRU algorithm
Operand Cache
16-kbyte cache or 8-kbyte cache +
8-kbyte RAM
Direct mapping
32 bytes
512
Copy-back/write-through selectable
Operand Cache
32-kbyte cache or 16-kbyte cache +
16-kbyte RAM
2-way set-associative
32 bytes
512 entries/way
Copy-back/write-through selectable
Rev. 6.0, 07/02, page 95 of 986