Section 4 Caches; Overview; Features - Hitachi SH7750 Programming Manual

High-performance risc engine superh (sh) 32-bit risc mcu/mpu series
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4.1

Overview

4.1.1

Features

The SH7750 has an on-chip 8-kbyte instruction cache (IC) for instructions and 16-kbyte operand
cache (OC) for data. Half of the memory of the operand cache (8 kbytes) can also be used as on-
chip RAM. The features of these caches are summarized in table 4.1.
Table 4.1
Cache Features
Item
Capacity
Type
Line size
Entries
Write method
Item
Capacity
Addresses
Write
Write-back
Access right

Section 4 Caches

Instruction Cache
8-kbyte cache
Direct mapping
32 bytes
256
Store Queues
2 × 32 bytes
H'E000 0000 to H'E3FF FFFF
Store instruction (1-cycle write)
Prefetch instruction
MMU off: according to MMUCR.SQMD
MMU on: according to individual page PR
Operand Cache
16-kbyte cache or 8-kbyte cache +
8-kbyte RAM
Direct mapping
32 bytes
512
Copy-back/write-through selectable
Rev. 2.0, 03/99, page 61 of 396

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