Fadd - Hitachi SH7750 Programming Manual

10.26

FADD

Floating-Point
Addition
PR Format
FADD FRm,FRn FRn+FRm → FRn
0
FADD DRm,DRn DRn+DRm → DRn
1
Description
When FPSCR.PR = 0: Arithmetically adds the two single-precision floating-point numbers in FRn
and FRm, and stores the result in FRn.
When FPSCR.PR = 1: Arithmetically adds the two double-precision floating-point numbers in
DRn and DRm, and stores the result in DRn.
When FPSCR.enable.O/U/I is set, an FPU exception trap is generated regardless of whether or not
an exception has occurred. When an exception occurs, correct exception information is reflected in
FPSCR.cause and FPSCR.flag, and FRn or DRn is not updated. Appropriate processing should
therefore be performed by software.
Operation
void FADD (int m,n)
{
pc += 2;
clear_cause();
if((data_type_of(m) == sNaN) ||
(data_type_of(n) == sNaN)) invalid(n);
else if((data_type_of(m) == qNaN) ||
(data_type_of(n) == qNaN)) qnan(n);
else if((data_type_of(m) == DENORM) ||
(data_type_of(n) == DENORM)) set_E();
else switch (data_type_of(m)){
case NORM: switch (data_type_of(n)){
case NORM:
case PZERO:
case NZERO:register_copy(m,n); break;
default:
}
Floating-point ADD
Summary of Operation
normal_faddsub(m,n,ADD); break;
break;
break;
Floating-Point Instruction
Instruction Code
1111nnnnmmmm0000 1
1111nnn0mmm00000 6
Rev. 2.0, 03/99, page 245 of 396
Execution
States T Bit
—
—