Shad - Hitachi SH7750 Programming Manual

High-performance risc engine superh (sh) 32-bit risc mcu/mpu series
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10.83

SHAD

Dynamic Arithmetic Shift
Format
SHAD Rm, Rn
Description
This instruction arithmetically shifts the contents of general register Rn. General register Rm
specifies the shift direction and the number of bits to be shifted.
Rn register contents are shifted to the left if the Rm register value is positive, and to the right if
negative. In a shift to the right, the MSB is added at the upper end.
The number of bits to be shifted is specified by the lower 5 bits (bits 4 to 0) of the Rm register. If
the value is negative (MSB = 1), the Rm register is represented as a two's complement. The left
shift range is 0 to 31, and the right shift range, 1 to 32.
Rm
Rm
SHift Arithmetic Dynamically
Summary of Operation
When Rm ≥ 0,
Rn << Rm → Rn
When Rm < 0,
Rn >> Rm → [MSB → Rn]
0
MSB
0
MSB
MSB
Instruction Code
0100nnnnmmmm1100 1
LSB
LSB
Rev. 2.0, 03/99, page 355 of 396
Shift Instruction
Execution
States
T Bit
0

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