Hitachi SH7750 Programming Manual page 119

(9) General Illegal Instruction Exception
• Sources:
 Decoding of an undefined instruction not in a delay slot
Delayed branch instructions: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT/S, BF/S
Undefined instruction: H'FFFD
 Decoding in user mode of a privileged instruction not in a delay slot
Privileged instructions: LDC, STC, RTE, LDTLB, SLEEP, but excluding LDC/STC
instructions that access GBR
• Transition address: VBR + H'0000 0100
• Transition operations:
The PC and SR contents for the instruction at which this exception occurred are saved in SPC
and SSR.
Exception code H'180 is set in EXPEVT. The BL, MD, and RB bits are set to 1 in SR, and a
branch is made to PC = VBR + H'0100. Operation is not guaranteed if an undefined code other
than H'FFFD is decoded.
General_illegal_instruction_exception()
{
SPC = PC;
SSR = SR;
EXPEVT = H'00000180;
SR.MD = 1;
SR.RB = 1;
SR.BL = 1;
PC = VBR + H'00000100;
}
Rev. 2.0, 03/99, page 105 of 396