Hitachi SH7750 Programming Manual page 380

High-performance risc engine superh (sh) 32-bit risc mcu/mpu series
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Operation
SHLR2(long n)
{
R[n]>>=2;
R[n]&=0x3FFFFFFF;
PC+=2;
}
SHLR8(long n)
{
R[n]>>=8;
R[n]&=0x00FFFFFF;
PC+=2;
}
SHLR16(long n)
{
R[n]>>=16;
R[n]&=0x0000FFFF;
PC+=2;
}
Example
SHLR2
R0
SHLR8
R0
SHLR16 R0
Rev. 2.0, 03/99, page 366 of 396
/* SHLR2 Rn */
/* SHLR8 Rn */
/* SHLR16 Rn */
;Before execution R0 = H'12345678
;After execution
R0 = H'048D159E
;Before execution R0 = H'12345678
;After execution
R0 = H'00123456
;Before execution R0 = H'12345678
;After execution
R0 = H'00001234

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