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10.31
FIPR
Floating-Point
Inner Product
PR
Format
0
FIPR FVm,FVn
—
—
Notes: FV0 = {FR0, FR1, FR2, FR3}
FV4 = {FR4, FR5, FR6, FR7}
FV8 = {FR8, FR9, FR10, FR11}
FV12 = {FR12, FR13, FR14, FR15}
Description
When FPSCR.PR = 0: This instruction calculates the inner products of the 4-dimensional single-
precision floating-point vector indicated by FVn and FVm, and stores the results in FR[n + 3].
The FIPR instruction is intended for speed rather than accuracy, and therefore the results will
differ from those obtained by using a combination of FADD and FMUL instructions. The FIPR
execution sequence is as follows:
1. Multiplies all terms. The results are 28 bits long.
2. Aligns these results, rounding them to fit within 30 bits.
3. Adds the aligned values.
4. Performs normalization and rounding.
Special processing is performed in the following cases:
1. If an input value is an sNaN, an invalid exception is generated.
2. If the input values to be multiplied include a combination of 0 and infinity, an invalid
exception is generated.
3. In cases other than the above, if the input values include a qNaN, the result will be a qNaN.
4. In cases other than the above, if the input values include infinity:
a. If multiplication results in two or more infinities and the signs are different, an invalid
exception will be generated.
b. Otherwise, correct infinities will be stored.
5. If the input values do not include an sNaN, qNaN, or infinity, processing is performed in the
normal way.
Rev. 2.0, 03/99, page 258 of 396
Floating-point Inner
PRoduct
Summary of Operation
FVn ⋅ FVm → FR[n+3]
—
Floating-Point Instruction
Instruction Code
1111nnmm11101101 1
—
Execution
States
T Bit
—
—
—
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