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3.3.3
Virtual Memory Space
Setting the MMUCR.AT bit to 1 enables the P0, P3, and U0 areas of the physical memory space in
the SH7750 to be mapped onto any external memory space in 1-, 4-, or 64-kbyte, or 1-Mbyte,
page units. By using an 8-bit address space identifier, the P0, U0, P3, and store queue areas can be
increased to a maximum of 256. This is called the virtual memory space. Mapping from virtual
memory space to 29-bit external memory space is carried out using the TLB. Only when area 7 in
external memory space is accessed using virtual memory space, addresses H'1F00 0000 to H'1FFF
FFFF of area 7 are not designated as a reserved area, but are equivalent to the P4 area control
register area in the physical memory space. Virtual memory space is illustrated in figure 3.6.
256
P0 area
Cacheable
Address translation possible
P1 area
Cacheable
Address translation not possible
P2 area
Non-cacheable
Address translation not possible
P3 area
Cacheable
Address translation possible
P4 area
Non-cacheable
Address translation not possible
Privileged mode
Figure 3.6 Virtual Memory Space (MMUCR.AT = 1)
P0, P3, U0 Areas: The P0 area (excluding addresses H'7C00 0000 to H'7FFF FFFF), P3 area, and
U0 area allow access using the cache and address translation using the TLB. These areas can be
mapped onto any external memory space in 1-, 4-, or 64-kbyte, or 1-Mbyte, page units. When
CCR is in the cache-enabled state and the TLB enable bit (C bit) is 1, accesses can be performed
using the cache. In write accesses to the cache, switching between the copy-back method and the
write-through method is indicated by the TLB write-through bit (WT bit), and is specified in page
units.
Rev. 2.0, 03/99, page 36 of 396
256
External
memory space
Area 0
Area 1
Area 2
Area 3
Area 4
Area 5
Area 6
Area 7
U0 area
Cacheable
Address translation possible
Address error
Store queue area
Address error
User mode
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