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(14) FPU Exception
• Source: Exception due to execution of a floating-point operation
• Transition address: VBR + H'0000 0100
• Transition operations:
The PC and SR contents for the instruction at which this exception occurred are saved in SPC
and SSR. Exception code H'120 is set in EXPEVT. The BL, MD, and RB bits are set to 1 in
SR, and a branch is made to PC = VBR + H'0100.
FPU_exception()
{
SPC = PC;
SSR = SR;
EXPEVT = H'00000120;
SR.MD = 1;
SR.RB = 1;
SR.BL = 1;
PC = VBR + H'00000100;
}
Rev. 2.0, 03/99, page 110 of 396
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