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10.6
BF/S
Conditional Branch with Delay
Format
BF/S label
Description
This is a delayed conditional branch instruction that references the T bit. If T = 1, the next
instruction is executed and the branch is not taken. If T = 0, the branch is taken after execution of
the next instruction.
The branch destination is address (PC + 4 + displacement × 2). The PC source value is the BF/S
instruction address. As the 8-bit displacement is multiplied by two after sign-extension, the branch
destination can be located in the range from –256 to +254 bytes from the BF/S instruction.
Notes
As this is a delayed branch instruction, when the branch condition is satisfied, the instruction
following this instruction is executed before the branch destination instruction.
Interrupts are not accepted between this instruction and the following instruction.
If the following instruction is a branch instruction, it is identified as a slot illegal instruction.
If this instruction is located in the delay slot immediately following a delayed branch instruction, it
is identified as a slot illegal instruction.
If the branch destination cannot be reached, the branch must be handled by using BF/S in
combination with a BF, BRA, or JMP instruction, for example.
Branch if False with delay Slot
Summary of Operation
If T = 0
PC + 4 + disp × 2 → PC
If T = 1, nop
Branch Instruction
Delayed Branch Instruction
Instruction Code
10001111dddddddd 1
Rev. 2.0, 03/99, page 209 of 396
Execution
States
T Bit
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