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10.61
MOVCA.L
Cache Block Allocation
Format
MOVCA.L R0,@Rn
Description
This instruction stores the contents of general register R0 in the memory location indicated by
effective address Rn. This instruction differs from other store instructions as follows.
If write-back is selected for the accessed memory, and a cache miss occurs, the cache block will
be allocated but an R0 data write will be performed to that cache block without performing a block
read. Other cache block contents are undefined.
Operation
MOVCAL(int n)
{
if ((is_write_back_memory(R[n]))
&& (look_up_in_operand_cache(R[n]) == MISS))
Write_Long(R[n], R[0]);
PC+=2;
}
Possible Exceptions:
• Data TLB miss exception
• Data TLB protection violation exception
• Initial page write exception
• Address error
Rev. 2.0, 03/99, page 330 of 396
MOVe with Cache
block Allocation
Summary of Operation
R0 → (Rn)
/*MOVCA.L
R0,@Rn */
allocate_operand_cache_block(R[n]);
Data Transfer Instruction
Instruction Code
0000nnnn11000011 1
Execution
States
T Bit
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