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From any state when
= 0 and
Interrupt
Bus-released state
Bus request
2.7
Processor Modes
There are two processor modes: user mode and privileged mode. The processor mode is
determined by the processor mode bit (MD) in the status register (SR). User mode is selected
when the MD bit is cleared to 0, and privileged mode when the MD bit is set to 1. When the reset
state or exception state is entered, the MD bit is set to 1. When exception handling ends, the MD
bit is cleared to 0 and user mode is entered. There are certain registers and bits which can only be
accessed in privileged mode.
From any state when
= 1
Power-on reset state
= 1,
Exception-handling state
Bus request
Bus request
clearance
Exception
interrupt
Bus request
Bus
clearance
request
Bus request
Program execution state
clearance
SLEEP instruction
with STBY bit
cleared
Sleep mode
Figure 2.6 Processor State Transitions
= 0 and
= 0,
= 1
= 1
End of exception
transition
processing
SLEEP instruction
with STBY bit set
= 0
Manual reset state
Reset state
= 1,
= 0
Standby mode
Power-down state
Rev. 2.0, 03/98, page 23 of 396
Interrupt
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