Hitachi SH7750 Programming Manual page 247

High-performance risc engine superh (sh) 32-bit risc mcu/mpu series
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}
break;
}
T=(Q==M);
PC+=2;
}
Example 1
SHLL16
R0
TST
R0,R0
BT
ZERO_DIV
CMP/HS
R0,R1
BT
OVER_DIV
DIV0U
.arepeat
16
DIV1
R0,R1
.aendr
ROTCL
R1
EXTU.W
R1,R1
R[n]-=tmp2;
tmp1=(R[n]>tmp0);
switch(Q){
case 0:Q=(unsigned char)(tmp1==0);
break;
case 1:Q=tmp1;
break;
}
break;
;R1 (32 bits) ÷ R0 (16 bits) = R1 (16 bits); unsigned
;Set divisor in upper 16 bits, clear lower 16 bits to 0
;Check for division by zero
;
;Check for overflow
;
;Flag initialization
;
;Repeat 16 times
;
;
;R1 = quotient
Rev. 2.0, 03/99, page 233 of 396

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