And - Hitachi SH7750 Programming Manual

High-performance risc engine superh (sh) 32-bit risc mcu/mpu series
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10.4

AND

Logical AND
Format
AND
Rm,Rn
AND
#imm,R0
AND.B #imm,@(R0,GBR) (R0+GBR) & imm →
Description
This instruction ANDs the contents of general registers Rn and Rm and stores the result in Rn.
This instruction can be used to AND general register R0 contents with zero-extended 8-bit
immediate data, or, in indexed GBR indirect addressing mode, to AND 8-bit memory with 8-bit
immediate data.
Notes
With AND #imm,R0, the upper 24 bits of R0 are always cleared as a result of the operation.
Operation
AND(long m, long n)
{
R[n]&=R[m];
PC+=2;
}
ANDI(long i)
{
R[0]&=(0x000000FF & (long)i);
PC+=2;
}
ANDM(long i)
{
long temp;
temp=(long)Read_Byte(GBR+R[0]);
AND logical
Summary of Operation
Rm & Rm → Rn
R0 & imm → R0
(R0+GBR)
/* AND Rm,Rn */
/* AND #imm,R0 */
/* AND.B #imm,@(R0,GBR) */
Logical Instruction
Instruction Code
0010nnnnmmmm1001 1
11001001iiiiiiii 1
11001101iiiiiiii 4
Rev. 2.0, 03/99, page 205 of 396
Execution
States
T Bit

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