10.101 Tst - Hitachi SH7750 Programming Manual

10.101 TST

AND Operation
T Bit Setting
Format
TST Rm,Rn
TST #imm,R0
TST.B #imm,@(R0,GBR) (R0 + GBR) & imm;
Description
This instruction ANDs the contents of general registers Rn and Rm, and sets the T bit if the result
is zero. If the result is nonzero, the T bit is cleared. The contents of Rn are not changed.
This instruction can be used to AND general register R0 contents with zero-extended 8-bit
immediate data, or, in indexed GBR indirect addressing mode, to AND 8-bit memory with 8-bit
immediate data. The contents of R0 or the memory are not changed.
Operation
TST(long m, long n) /* TST Rm,Rn */
{
if ((R[n]&R[m])==0) T=1;
else T=0;
PC+=2;
}
TSTI(long i) /* TST #imm,R0 */
{
long temp;
temp=R[0]&(0x000000FF & (long)i);
if (temp==0) T=1;
else T=0;
PC+=2;
}
Rev. 2.0, 03/99, page 386 of 396
TeST logical
Summary of Operation
Rn & Rm; if result is 0,
1 → T, else 0 → T
R0 & imm; if result is 0,
1 → T, else 0 → T
if result is 0, 1 → T,
else 0 → T
Logical Instruction
Instruction Code
0010nnnnmmmm1000 1
11001000iiiiiiii 1
11001100iiiiiiii 3
Execution
States T Bit
Test
result
Test
result
Test
result