Mac.w - Hitachi SH7750 Programming Manual

High-performance risc engine superh (sh) 32-bit risc mcu/mpu series
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10.55

MAC.W

Single-Precision
Multiply-and-Accumulate
Operation
Format
MAC.W @Rm+,@Rn+
MAC
@Rm+,@Rn+
Description
This instruction performs signed multiplication of the 16-bit operands whose addresses are the
contents of general registers Rm and Rn, adds the 32-bit result to the MAC register contents, and
stores the result in the MAC register. Operands Rm and Rn are each incremented by 2 each time
they are read.
If the S bit is 0, a 16 × 16 + 64 → 64-bit multiply-and-accumulate operation is performed, and the
64-bit result is stored in the linked MACH and MACL registers.
If the S bit is 1, a 16 × 16 + 32 → 32-bit multiply-and-accumulate operation is performed, and the
addition to the MAC register contents is a saturation operation. In a saturation operation, only the
MACL register is valid, and the result range is limited to H'80000000 (minimum value) to
H'7FFFFFFF (maximum value). If overflow occurs, the LSB of the MACH register is set to 1.
H'80000000 (minimum value) is stored in the MACL register if the result overflows in the
negative direction, and H'7FFFFFFF (maximum value) is stored if the result overflows in the
positive direction
Notes
If the S bit is 0, a 16 × 16 + 64 → 64-bit multiply-and-accumulate operation is performed.
Rev. 2.0, 03/99, page 312 of 396
Multiply and
ACcumulate Word
Summary of Operation
Signed,
(Rn) × (Rm) + MAC →MAC
Rn + 2 → Rn, Rm + 2 → Rm
Arithmetic Instruction
Instruction Code
0100nnnnmmmm1111 2–5
Execution
States
T Bit

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