Fneg - Hitachi SH7750 Programming Manual

10.40

FNEG

Floating-Point
Sign Inversion
PR Format
0 FNEG FRn
1 FNEG DRn
Description
This instruction inverts the most significant bit (sign bit) of the contents of floating-point register
FRn/DRn, and stores the result in FRn/DRn.
The cause and flag fields in FPSCR are not updated.
Operation
void FNEG (int n){
FR[n] = -FR[n];
pc += 2;
}
/* Same operation is performed regardless of precision. */
Possible Exceptions:
None
Rev. 2.0, 03/99, page 280 of 396
Floating-point NEGate value Floating-Point Instruction
Summary of Operation
-FRn → FRn
-DRn → DRn
Instruction Code
1111nnnn01001101 1
1111nnn001001101 1
Execution
States T Bit
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