Table of Contents
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1.1
SH7750 Features...............................................................................................................
1.2
Block Diagram..................................................................................................................
2.1
Data Formats.....................................................................................................................
2.2
Register Configuration...................................................................................................... 10
2.2.1
Privileged Mode and Banks................................................................................. 10
2.2.2
General Registers................................................................................................. 13
2.2.3
Floating-Point Registers ...................................................................................... 15
2.2.4
Control Registers ................................................................................................. 17
2.2.5
System Registers.................................................................................................. 18
2.3
Memory-Mapped Registers .............................................................................................. 20
2.4
Data Format in Registers .................................................................................................. 21
2.5
Data Formats in Memory.................................................................................................. 21
2.6
Processor States ................................................................................................................ 22
2.7
Processor Modes............................................................................................................... 23
3.1
Overview .......................................................................................................................... 25
3.1.1
Features................................................................................................................ 25
3.1.2
Role of the MMU ................................................................................................ 25
3.1.3
Register Configuration......................................................................................... 28
3.1.4
Caution ................................................................................................................ 28
3.2
Register Descriptions........................................................................................................ 29
3.3
Memory Space .................................................................................................................. 32
3.3.1
Physical Memory Space ...................................................................................... 32
3.3.2
External Memory Space ...................................................................................... 35
3.3.3
Virtual Memory Space......................................................................................... 36
3.3.4
On-Chip RAM Space........................................................................................... 37
3.3.5
Address Translation............................................................................................. 37
3.3.6
Single Virtual Memory Mode and Multiple Virtual Memory Mode ................... 38
3.3.7
Address Space Identifier (ASID)......................................................................... 38
3.4
TLB Functions .................................................................................................................. 38
3.4.1
Unified TLB (UTLB) Configuration ................................................................... 38
3.4.2
Instruction TLB (ITLB) Configuration................................................................ 42
3.4.3
Address Translation Method................................................................................ 42
3.5
MMU Functions................................................................................................................ 45
3.5.1
MMU Hardware Management............................................................................. 45
Contents
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Rev. 2.0, 03/99, page vii of 13
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