Table of Contents
Advertisement
10.12
BT/S
Conditional Branch with Delay
Format
BT/S label
Description
This is a conditional branch instruction that references the T bit. The branch is taken if T = 1, and
not taken if T = 0.
The PC source value is the BT/S instruction address. As the 8-bit displacement is multiplied by
two after sign-extension, the branch destination can be located in the range from –256 to +254
bytes from the BT/S instruction. If the branch destination cannot be reached, the branch must be
handled by using BT/S in combination with a BRA or JMP instruction, for example.
Notes
As this is a delayed branch instruction, when the branch condition is satisfied, the instruction
following this instruction is executed before the branch destination instruction.
Interrupts are not accepted between this instruction and the following instruction.
If the following instruction is a branch instruction, it is identified as a slot illegal instruction.
Rev. 2.0, 03/99, page 220 of 396
Branch if True with delay Slot
Summary of Operation
If T = 1
PC + 4 + disp × 2 → PC
If T = 0, nop
Branch Instruction
Delayed Branch Instruction
Instruction Code
10001101dddddddd 1
Execution
States
T Bit
—
Advertisement
Table of Contents
