Hitachi SH7750 Programming Manual page 315

High-performance risc engine superh (sh) 32-bit risc mcu/mpu series
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LDCMSSR(int m)
{
SSR=Read_Long(R[m]);
R[m]+=4;
PC+=2;
}
LDCMSPC(int m)
{
SPC=Read_Long(R[m]);
R[m]+=4;
PC+=2;
}
LDCMDBR(int m)
{
DBR=Read_Long(R[m]);
R[m]+=4;
PC+=2;
}
LDCMRn_BANK(Long m) /* LDC.L @Rm+,Rn_BANK : Privileged */
{
Rn_BANK=Read_Long(R[m]);
R[m]+=4;
PC+=2;
}
Possible Exceptions:
• General illegal instruction exception
• Illegal slot instruction exception
• Data TLB miss exception
• Data TLB protection violation exception
• Address error
/* LDC.L @Rm+,SSR : Privileged */
/* LDC.L @Rm+,SPC : Privileged */
/* LDC.L @Rm+,DBR : Privileged */
/* n=0–7 */
Rev. 2.0, 03/99, page 301 of 396

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