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4.6
Store Queues
Two 32-byte store queues (SQs) are supported to perform high-speed writes to external memory.
4.6.1
SQ Configuration
There are two 32-byte store queues, SQ0 and SQ1, as shown in figure 4.10. These two store
queues can be set independently.
SQ0[0]
SQ0
SQ1[0]
SQ1
4B
4.6.2
SQ Writes
A write to the SQs can be performed using a store instruction (MOV) on P4 area H'E000 0000 to
H'E3FF FFFC. A longword or quadword access size can be used. The meaning of the address bits
is as follows:
[31:26]:
111000
[25:6]:
Don't care
[5]:
0/1
[4:2]:
LW specification
[1:0]
00
4.6.3
Transfer to External Memory
Transfer from the SQs to external memory can be performed with a prefetch instruction (PREF).
Issuing a PREF instruction for P4 area H'E000 0000 to H'E3FF FFFC starts a burst transfer from
the SQs to external memory. The burst transfer length is fixed at 32 bytes, and the start address is
always at a 32-byte boundary. While the contents of one SQ are being transferred to external
memory, the other SQ can be written to without a penalty cycle, but writing to the SQ involved in
the transfer to external memory is deferred until the transfer is completed.
The SQ transfer destination external memory address bit [28:0] specification is as shown below,
according to whether the MMU is on or off.
SQ0[1]
SQ0[2]
SQ0[3]
SQ1[1]
SQ1[2]
SQ1[3]
4B
4B
Figure 4.10 Store Queue Configuration
Store queue specification
Used for external memory transfer/access right
0: SQ0 specification
Specifies longword position in SQ0/SQ1
Fixed at 0
SQ0[4]
SQ0[5]
SQ1[4]
SQ1[5]
4B
4B
4B
1: SQ1 specification
SQ0[6]
SQ0[7]
SQ1[6]
SQ1[7]
4B
4B
Rev. 2.0, 03/99, page 79 of 396
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