Table 22.31 Clock And Control Signal Timing; Hd6417750Sf167, Hd6417750Sf167I) - Hitachi SH7750 Hardware Manual

Table 22.31 Clock and Control Signal Timing (HD6417750F167, HD6417750F167I,

HD6417750SF167, HD6417750SF167I)

HD6417750SF167, HD6417750F167: V
HD6417750SF167I, HD6417750F167I: V
Item
EXTAL PLL2
clock input operating
frequency
PLL2 not
operating
EXTAL clock input cycle time
EXTAL clock input low-level pulse width
EXTAL clock input high-level pulse width t
EXTAL clock input rise time
EXTAL clock input fall time
CKIO clock PLL2 operating
output
PLL2 not operating
CKIO clock output cycle time
CKIO clock output low-level pulse width
CKIO clock output high-level pulse width
CKIO clock output rise time
CKIO clock output fall time
CKIO clock output low-level pulse width
CKIO clock output high-level pulse width
Power-on oscillation settling time
Power-on oscillation settling time/mode
settling
SCK2 reset setup time
SCK2 reset hold time
MD reset setup time
MD reset hold time
Rev. 6.0, 07/02, page 856 of 986
= 3.0 to 3.6 V, V
DDQ
C = 30 pF
L
= 3.0 to 3.6 V, V
DDQ
C = 30 pF
L
Symbol
1/2 divider f
EX
operating
1/2 divider not f
EX
operating
1/2 divider f
EX
operating
1/2 divider not f
EX
operating
t
EXcyc
t
EXL
EXH
t
EXr
t
EXf
f
OP
f
OP
t
cyc
t
CKOL1
t
CKOH1
t
CKOr
t
CKOf
t
CKOL2
t
CKOH2
t
OSC1
t
OSCMD
t
SCK2RS
t
SCK2RH
t
MDRS
t
MDRH
= 1.8 V, T
DD a
= 1.8 V, T
DD a
Min Max Unit
16 56 MHz
8 28
2 56
1 28
18 1000 ns
3.5 — ns
3.5 — ns
— 4 ns
— 4 ns
25 84 MHz
1 84 MHz
12 1000 ns
1 — ns
1 — ns
— 3 ns
— 3 ns
3 — ns
3 — ns
10 — ms
10 — ms
20 — ns
20 — ns
3 — t
cyc
20 — ns
= –20 to +75°C,
= –40 to +85°C,
Figure
22.1
22.1
22.1
22.1
22.1
22.2(1)
22.2(1)
22.2(1)
22.2(1)
22.2(1)
22.2(2)
22.2(2)
22.3, 22.5
22.3, 22.5
22.11
22.3, 22.5, 22.11
22.12
22.3, 22.5, 22.12