Hitachi SH7750 Hardware Manual page 854

SH7750R:
Bit:
Initial value:
R/W:
Bit:
Initial value:
R/W:
Bits 15 to 8—Test Instruction Bits (TI7–TI0)
Bit 15: Bit 14: Bit 13:
TI7 TI6 TI5
0 0 0
0 0 0
0 1 1
0 1 1
1 0 1
1 1 1
Other than above
Bits 7 to 0—Reserved: These bits are always read as 1, and should only be written with 1.
Rev. 6.0, 07/02, page 804 of 986
15 14 13
TI7 TI6 TI5
1 1 1
R R R
7 6 5
— — —
1 1 1
R R R
Bit 12: Bit 11: Bit 10:
TI4 TI3 TI2
0 0 0
0 0 1
0 — —
1 — —
— — —
1 1 1
12 11 10
TI4 TI3 TI2
1 1
R R
4 3
— — —
1 1
R R
Bit 9: Bit 8: Description
TI1 TI0
0 0 EXTEST
0 0 SAMPLE/PRELOAD
— — H-UDI reset negate
— — H-UDI reset assert
— — H-UDI interrupt
1 1 Bypass mode (Initial value)
Reserved
9 8
TI1 TI0
1 1 1
R R R
2 1 0
— —
1 1 1
R R R