Hitachi SH7750 Hardware Manual page 365

Table 13.1 BSC Pins (cont)
Name Signals
WE1/CAS1/
Data enable 1
DQM1
WE2/CAS2/
Data enable 2
DQM2/ICIORD
WE3/CAS3/
Data enable 3
DQM3/ICIOWR
WE4/CAS4/
Data enable 4
DQM4
WE5/CAS5/
Data enable 5
DQM5
I/O Description
O When setting synchronous DRAM interface:
selection signal for D15–D8
When setting DRAM interface: CAS signal for
D15–D8
When setting PCMCIA interface: write strobe signal
When setting MPX interface: high-level output
In other cases: write strobe signal for D15–D8
O When setting synchronous DRAM interface:
selection signal for D23–D16
When setting DRAM interface: CAS signal for
D23–D16
When setting PCMCIA interface: ICIORD signal
When setting MPX interface: high-level output
In other cases: write strobe signal for D23–D16
O When setting synchronous DRAM interface:
selection signal for D31–D24
When setting DRAM interface: CAS signal for
D31–D24
When setting PCMCIA interface: ICIOWR signal
When setting MPX interface: high-level output
In other cases: write strobe signal for D31–D24
O When setting synchronous DRAM interface:
selection signal for D39–D32
When setting DRAM interface: CAS signal for
D39–D32
When setting MPX interface: high-level output
In other cases: write strobe signal for D39–D32
O When setting synchronous DRAM interface:
selection signal for D47–D40
When setting DRAM interface: CAS signal for
D47–D40
When setting MPX interface: high-level output
In other cases: write strobe signal for D47–D40
Rev. 6.0, 07/02, page 315 of 986