Register Descriptions; Standby Control Register (Stbcr) - Hitachi SH7750 Hardware Manual

9.2

Register Descriptions

9.2.1

Standby Control Register (STBCR)

The standby control register (STBCR) is an 8-bit readable/writable register that specifies the
power-down mode status. It is initialized to H'00 by a power-on reset via the RESET pin or due to
watchdog timer overflow.
Bit:
Initial value:
R/W:
Bit 7—Standby (STBY): Specifies a transition to standby mode.
Bit 7: STBY
0
1
Bit 6—Peripheral Module Pin High Impedance Control (PHZ): Controls the state of
peripheral module related pins in standby mode. When the PHZ bit is set to 1, peripheral module
related pins go to the high-impedance state in standby mode.
For the relevant pins, see section 9.2.2, Peripheral Module Pin High Impedance Control.
Bit 6: PHZ
0
1
Bit 5—Peripheral Module Pin Pull-Up Control (PPU): Controls the state of peripheral module
related pins. When the PPU bit is cleared to 0, the pull-up resistor is turned on for peripheral
module related pins in the input or high-impedance state.
For the relevant pins, see section 9.2.3, Peripheral Module Pin Pull-Up Control.
Bit 5: PPU
0
1
Bit 4—Module Stop 4 (MSTP4): Specifies stopping of the clock supply to the DMAC among the
on-chip peripheral modules. The clock supply to the DMAC is stopped when the MSTP4 bit is set
Rev. 6.0, 07/02, page 224 of 986
7 6
STBY PHZ PPU
0 0
R/W R/W R/W
Description
Transition to sleep mode on execution of SLEEP instruction
Transition to standby mode on execution of SLEEP instruction
Description
Peripheral module related pins are in normal state
Peripheral module related pins go to high-impedance state
Description
Peripheral module related pin pull-up resistors are on
Peripheral module related pin pull-up resistors are off
5 4 3
MSTP4 MSTP3
0 0 0
R/W R/W
2 1
MSTP2 MSTP1 MSTP0
0 0
R/W R/W
(Initial value)
(Initial value)
(Initial value)
0
0
R/W