Hitachi SH7750 Hardware Manual page 810

Table 19.5 Interrupt Exception Handling Sources and Priority Order (cont)
Interrupt Source
2
TUNI3 *
TMU3
2
TUNI4 *
TMU4
TMU0 TUNI0
TMU1 TUNI1
TMU2 TUNI2
TICPI2
RTC ATI
PRI
CUI
SCI1 ERI
RXI
TXI
TEI
SCIF ERI
RXI
BRI
TXI
WDT ITI
REF RCMI
ROVI
Notes: TUNI0–TUNI4: Underflow interrupts
TICPI2: Input capture interrupt
ATI: Alarm interrupt
PRI: Periodic interrupt
CUI: Carry-up interrupt
ERI: Receive-error interrupt
RXI: Receive-data-full interrupt
TXI: Transmit-data-empty interrupt
TEI: Transmit-end interrupt
BRI: Break interrupt request
ITI: Interval timer interrupt
RCMI: Compare-match interrupt
ROVI: Refresh counter overflow interrupt
Rev. 6.0, 07/02, page 760 of 986
INTEVT Interrupt Priority
Code (Initial Value)
H'B00 15–0 (0)
H'B80 15–0 (0)
H'400 15–0 (0)
H'420 15–0 (0)
H'440 15–0 (0)
H'460
H'480 15–0 (0)
H'4A0
H'4C0
H'4E0 15–0 (0)
H'500
H'520
H'540
H'700 15–0 (0)
H'720
H'740
H'760
H'560 15–0 (0)
H'580 15–0 (0)
H'5A0
IPR (Bit Priority within
Numbers) IPR Setting Unit
INTPRI00 —
(11–8)
INTPRI00 —
(15–12)
IPRA (15–12) —
IPRA (11–8) —
IPRA (7–4) High
Low
IPRA (3–0) High
↑

↓
Low
IPRB (7–4) High
↑


↓
Low
IPRC (7–4) High
↑


↓
Low
IPRB (15–12) —
IPRB (11–8) High
Low
Default
Priority
High
↑









































↓
Low