Table 13.8 32-Bit External Device/Big-Endian Access And Data Alignment - Hitachi SH7750 Hardware Manual

Table 13.8 32-Bit External Device/Big-Endian Access and Data Alignment

Operation
Access
Size Address No. D31–D24 D23–D16 D15–D8 D7–D0
Byte 4n 1
4n+1 1
4n+2 1
4n+3 1
Word 4n 1
4n+2 1
Long- 4n 1
word
Quad- 8n 1
word
8n+4 2
Rev. 6.0, 07/02, page 374 of 986
Data Bus
Data — —
7–0
— Data —
7–0
— — Data
7–0
— — —
Data Data —
15–8 7–0
— — Data
15–8
Data Data Data
31–24 23–16 15–8
Data Data Data
63–56 55–48 47–40
Data Data Data
31–24 23–16 15–8
WE3 WE3, WE3 WE3 WE2, WE2 WE2 WE2
CAS3, CAS3 CAS3 CAS3 CAS2, CAS2 CAS2 CAS2
DQM3 DQM2
— Asserted
— Asserted
—
Data
7–0
— Asserted Asserted
Data
7–0
Data Asserted Asserted Asserted Asserted
7–0
Data Asserted Asserted Asserted Asserted
39–32
Data Asserted Asserted Asserted Asserted
7–0
Strobe Signals
WE1 WE1, WE1 WE1 WE0, WE0 WE0 WE0
CAS1, CAS1 CAS1 CAS1 CAS0, CAS0 CAS0 CAS0
DQM1 DQM0
Asserted
Asserted
Asserted Asserted