Hitachi SH7750 Hardware Manual page 275

to 1. When DMA transfer is used, stop the transfer before setting the MSTP4 bit to 1. When DMA
transfer is performed after clearing the MSTP4 bit to 0, DMAC settings must be made again.
Bit 4: MSTP4
0
1
Bit 3—Module Stop 3 (MSTP3): Specifies stopping of the clock supply to serial communication
interface channel 2 (SCIF) among the on-chip peripheral modules. The clock supply to the SCIF is
stopped when the MSTP3 bit is set to 1.
Bit 3: MSTP3
0
1
Bit 2—Module Stop 2 (MSTP2): Specifies stopping of the clock supply to the timer unit (TMU)
among the on-chip peripheral modules. The clock supply to the TMU is stopped when the MSTP2
bit is set to 1.
Bit 2: MSTP2
0
1
Bit 1—Module Stop 1 (MSTP1): Specifies stopping of the clock supply to the realtime clock
(RTC) among the on-chip peripheral modules. The clock supply to the RTC is stopped when the
MSTP1 bit is set to 1. When the clock supply is stopped, RTC registers cannot be accessed but the
counters continue to operate.
Bit 1: MSTP1
0
1
Bit 0—Module Stop 0 (MSTP0): Specifies stopping of the clock supply to serial communication
interface channel 1 (SCI) among the on-chip peripheral modules. The clock supply to the SCI is
stopped when the MSTP0 bit is set to 1.
Bit 0: MSTP0
0
1
Description
DMAC operates
DMAC clock supply is stopped
Description
SCIF operates
SCIF clock supply is stopped
Description
TMU operates
TMU clock supply is stopped
Description
RTC operates
RTC clock supply is stopped
Description
SCI operates
SCI clock supply is stopped
(Initial value)
(Initial value)
(Initial value)
(Initial value)
(Initial value)
Rev. 6.0, 07/02, page 225 of 986