Hitachi SH7750 Hardware Manual page 46

Figure 22.67 TCK Input Timing ........................................................................................... 932
RESET Hold Timing........................................................................................ 932
Figure 22.68
Figure 22.69 H-UDI Data Transfer Timing .......................................................................... 933
Figure 22.70 Pin Break Timing............................................................................................. 933
Figure 22.71 NMI Input Timing ........................................................................................... 933
Figure 22.72 Output Load Circuit ......................................................................................... 934
Figure 22.73 Load Capacitance vs. Delay Time ................................................................... 935
Figure B.1 Package Dimensions (256-Pin BGA) (SH7750 and SH7750S) ....................... 943
Figure B.2 Package Dimensions (256-Pin BGA) (SH7750R Only) .................................. 944
Figure B.3 Package Dimensions (208-Pin QFP)................................................................ 945
Figure B.4 Package Dimensions (264-Pin CSP)................................................................ 946
CKIO2ENB Pin Configuration ........................................................................ 949
Figure D.1
Figure G.1 Instruction Prefetch.......................................................................................... 977
Figure H.1 Power-On and Power-Off Procedures.............................................................. 978
Tables
Table 1.1 SH7750 Series Features .....................................................................................
Table 1.2 Pin Functions ..................................................................................................... 13
Table 1.3 Pin Functions ..................................................................................................... 23
Table 1.4 Pin Functions ..................................................................................................... 31
Table 2.1 Initial Register Values........................................................................................ 43
Table 3.1 MMU Registers.................................................................................................. 60
Table 4.1 Cache Features (SH7750, SH7750S) ................................................................. 95
Table 4.2 Cache Features (SH7750R)................................................................................ 95
Table 4.3 Features of Store Queues ................................................................................... 96
Table 4.4 Cache Control Registers .................................................................................... 96
Table 5.1 Exception-Related Registers .............................................................................. 127
Table 5.2 Exceptions.......................................................................................................... 130
Table 5.3 Types of Reset ................................................................................................... 137
Table 6.1 Floating-Point Number Formats and Parameters ............................................... 162
Table 6.2 Floating-Point Ranges........................................................................................ 163
Table 7.1 Addressing Modes and Effective Addresses...................................................... 175
Table 7.2 Notation Used in Instruction List....................................................................... 179
Table 7.3 Fixed-Point Transfer Instructions ...................................................................... 180
Table 7.4 Arithmetic Operation Instructions ..................................................................... 182
Table 7.5 Logic Operation Instructions ............................................................................. 184
Table 7.6 Shift Instructions................................................................................................ 185
Table 7.7 Branch Instructions ............................................................................................ 186
Table 7.8 System Control Instructions............................................................................... 187
Table 7.9 Floating-Point Single-Precision Instructions ..................................................... 189
Table 7.10 Floating-Point Double-Precision Instructions.................................................... 190
Table 7.11 Floating-Point Control Instructions ................................................................... 190
Rev. 6.0, 07/02, page xlvi of I
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