Exception Types And Priorities; Figure 21.3 H-Udi Reset; Table 5.2 Exceptions - Hitachi SH7750 Hardware Manual

Sh7750 series superh risc engine
Hide thumbs Also See for SH7750:
Table of Contents

Advertisement

5.4

Exception Types and Priorities

Table 5.2 shows the types of exceptions, with their relative priorities, vector addresses, and
exception/interrupt codes.
Table 5.2
Exceptions
Exception
Execution
Category
Mode
Reset
Abort type
General
Re-
exception
execution
type
Completion
type
Rev. 6.0, 07/02, page 130 of 986
Exception
Power-on reset
Manual reset
H-UDI reset
Instruction TLB multiple-hit
exception
Data TLB multiple-hit exception 1
User break before instruction
1
execution *
Instruction address error
Instruction TLB miss exception
Instruction TLB protection
violation exception
General illegal instruction
exception
Slot illegal instruction exception 2
General FPU disable exception 2
Slot FPU disable exception
Data address error (read)
Data address error (write)
Data TLB miss exception (read) 2
Data TLB miss exception (write) 2
Data TLB protection
violation exception (read)
Data TLB protection
violation exception (write)
FPU exception
Initial page write exception
Unconditional trap (TRAPA)
User break after instruction
execution *
1
Priority
Priority
Vector
Level
Order
Address
1
1
H'A000 0000 —
1
2
H'A000 0000 —
1
1
H'A000 0000 —
1
3
H'A000 0000 —
4
H'A000 0000 —
2
0
(VBR/DBR)
2
1
(VBR)
2
2
(VBR)
2
3
(VBR)
2
4
(VBR)
4
(VBR)
4
(VBR)
2
4
(VBR)
2
5
(VBR)
2
5
(VBR)
6
(VBR)
6
(VBR)
2
7
(VBR)
2
7
(VBR)
2
8
(VBR)
2
9
(VBR)
2
4
(VBR)
2
10
(VBR/DBR)
Exception
Offset
Code
H'000
H'020
H'000
H'140
H'140
H'100/— H'1E0
H'100
H'0E0
H'400
H'040
H'100
H'0A0
H'100
H'180
H'100
H'1A0
H'100
H'800
H'100
H'820
H'100
H'0E0
H'100
H'100
H'400
H'040
H'400
H'060
H'100
H'0A0
H'100
H'0C0
H'100
H'120
H'100
H'080
H'100
H'160
H'100/— H'1E0

Advertisement

Table of Contents
loading

This manual is also suitable for:

Sh7750rSh7750s

Table of Contents