Figure 4.7 Configuration Of Instruction Cache (Sh7750R) - Hitachi SH7750 Hardware Manual

Effective address
31 25
IIX
Entry
selection
22
8
MMU
19
255
Compare

Figure 4.7 Configuration of Instruction Cache (SH7750R)

• Tag
Stores the upper 19 bits of the 29-bit external address of the data line to be cached. The tag is
not initialized by a power-on or manual reset.
• V bit (validity bit)
Indicates that valid data is stored in the cache line. When this bit is 1, the cache line data is
valid. The V bit is initialized to 0 by a power-on reset, but retains its value in a manual reset.
• Data array
The data field holds 32 bytes (256 bits) of data per cache line. The data array is not initialized
by a power-on or manual reset.
Rev. 6.0, 07/02, page 110 of 986
[12]
Address array
(way 0, way1)
Tag address V
0
19 bits 1 bit
Compare
way 0 way 1
Hit signal
13 12 11 10
[11:5]
Longword (LW)
selection
Data array (way 0, way 1)
3
LW0 LW1 LW2
32 bits 32 bits 32 bits 32 bits
5 4 2 0
LW3 LW4 LW5 LW6
32 bits 32 bits 32 bits 32 bits
Read data
LRU
LW7
1 bit